Emulating biological synaptic characteristics of HfOx/AlN-based 3D vertical resistive memory for neuromorphic systems.

Here, we demonstrate double-layer 3D vertical resistive random-access memory with a hole-type structure embedding Pt/HfOx/AlN/TiN memory cells, conduct analog resistive switching, and examine the potential of memristors for use in neuromorphic systems. The electrical characteristics, including resistive switching, retention, and endurance, of each layer are also obtained. Additionally, we investigate various synaptic characteristics, such as spike-timing dependent plasticity, spike-amplitude dependent plasticity, spike-rate dependent plasticity, spike-duration dependent plasticity, and spike-number dependent plasticity. This synapse emulation holds great potential for neuromorphic computing applications. Furthermore, potentiation and depression are manifested through identical pulses based on DC resistive switching. The pattern recognition rates within the neural network are evaluated, and based on the conductance changing linearly with incremental pulses, we achieve a pattern recognition accuracy of over 95%. Finally, the device's stability and synapse characteristics exhibit excellent potential for use in neuromorphic systems.

High-Density 1R/1W Dual-Port Spin-Transfer Torque MRAM.

Spin-transfer torque magnetic random-access memory (STT-MRAM) has several desirable features, such as non-volatility, high integration density, and near-zero leakage power. However, it is challenging to adopt STT-MRAM in a wide range of memory applications owing to the long write latency and a tradeoff between read stability and write ability. To mitigate these issues, an STT-MRAM bit cell can be designed with two transistors to support multiple ports, as well as the independent optimization of read stability and write ability. The multi-port STT-MRAM, however, is achieved at the expense of a higher area requirement due to an additional transistor per cell. In this work, we propose an area-efficient design of 1R/1W dual-port STT-MRAM that shares a bitline between two adjacent bit cells. We identify that the bitline sharing may cause simultaneous access conflicts, which can be effectively alleviated by using the bit-interleaving architecture with a long interleaving distance and the sufficient number of word lines per memory bank. We report various metrics of the proposed design based on the bit cell design using a 45 nm process. Compared to a standard single-port STT-MRAM, the proposed design shows a 15% lower read power and a 19% higher read-disturb margin. Compared with prior work on the 1R/1W dual-port STT-MRAM, the proposed design improves the area by 25%.